The present invention relates to methods of semiconductor fabrication. In particular, the present invention relates to methods of forming copper metallization structures.
In the field of semiconductor fabrication techniques, an industry-wide transition from aluminum to copper interconnects is in progress. Currently, copper interconnects are formed using a so-called xe2x80x9cdamascenexe2x80x9d or xe2x80x9cdual-damascenexe2x80x9d fabrication process. Briefly, a damascene metallization process forms conducting interconnects by the deposition of conducting metals in recesses formed on a semiconductor wafer surface. Typically, semiconductor devices (e.g., transistors) are formed on a semiconductor substrate. These devices are typically covered with an oxide layer. Material is removed from selected regions of the oxide layer creating openings in the semiconductor substrate surface. The openings correspond to a circuit interconnect pattern forming an xe2x80x9cin-laidxe2x80x9d circuit pattern. This creates a semiconductor substrate having an in-laid circuit pattern corresponding to a conductor wiring pattern. Once the in-laid patterns have been formed in the oxide layer a barrier layer is formed, upon which, a conducting xe2x80x9cseed layerxe2x80x9d is fabricated. Such seed layers are frequently constructed of copper. This so-called seed layer provides a conducting foundation for a subsequently formed bulk copper interconnect layer which is usually formed by electroplating. After the bulk copper has been deposited excess copper is removed using, for example, chemical-mechanical polishing. The surface is then cleaned and sealed with a sealing layer. Further processing may then be performed.
Currently, the barrier layer is deposited over an etched substrate using physical vapor deposition (PVD) or chemical vapor deposition (CVD) techniques. Commonly used barrier materials are tantalum nitride, tungsten nitride, titanium nitride or silicon compounds of those materials. Barrier layer deposition by PVD has the advantage of creating barrier layer films of high purity and uniform chemical composition. The drawback of PVD techniques is the difficulty in obtaining good step coverage (a layer which evenly covers the underlying substrate is said to have good step coverage). On the other hand, CVD techniques or metal organic chemical vapor deposition (MOCVD) techniques provide excellent step coverage, even in narrow trenches having high aspect ratios (aspect ratio is the ratio of trench depth to trench width). The trade off with CVD and MOCVD techniques is that these processes are xe2x80x9cdirtyxe2x80x9d in comparison to PVD techniques. CVD and MOCVD incorporate large amounts of carbon and oxygen impurities into deposited films and are hence xe2x80x9cdirty.xe2x80x9d These impurities reduce the adhesion of the barrier layer to the underlying substrate. Similarly, the impurities reduce the adhesion of a subsequently formed seed layer to the barrier layer. This results in reduced film quality, void creation, increased electromigration problems, and reduced circuit reliability. Thus, a process engineer is faced with a delicate balancing act when choosing a deposition technique to form barrier layers.
After barrier layer deposition, a seed layer of conducting material is deposited. Typically, this material is copper, but other conducting materials may be used. The seed layer provides a low resistance conduction path for a plating current used in the electro-deposition of a subsequent bulk copper interconnect layer. Additionally, the seed layer provides a nucleation layer for the initiation of the subsequent electroplating of the bulk copper interconnect layer. Copper is the preferred seed layer material not only because of its high conductivity, but because it is the ideal nucleation layer for the growth of the subsequently electro-deposited copper film. The seed layer carries electroplating current from the edge of the wafer to the center, allowing the plating current source to contact the wafer only near the edge. The thickness of the seed layer must be sufficient such that the voltage drop from wafer edge to wafer center does not negatively impact the uniformity of the plating process. Additionally, the seed layer carries current into the bottom of vias and trenches. The thickness of the seed layer must be sufficient such that any voltage drop does not significantly retard the plating process at the bottom of the via or the trench relative to the top.
As with the barrier layer, the copper seed layer may be deposited using PVD, CVD, or MOCVD techniques. Seed layer deposition suffers from the same limitations as barrier layer deposition. When using PVD, the uneven step coverage in the seed layer results in an excessively thick copper seed layer near the top of trench structures while trench sidewalls and bottoms have a relatively thinner coating of copper film. This results in a xe2x80x9cpinching-offxe2x80x9d of the bottom of the trench during subsequent plating steps, leading to the existence of large voids and poor quality interconnect and via structures.
As explained above, step coverage problems inherent in PVD processes may be overcome using MOCVD or CVD techniques. MOCVD and CVD of copper are attractive because they are capable of depositing the seed layer at nearly 100 percent step coverage. This results in copper film of nearly uniform thickness throughout a wide range of surface conformations. As with the barrier layer, this advantage is especially useful in narrow trenches with high aspect ratios.
Unfortunately, when using a highly reactive substance such as copper, CVD and MOCVD become even xe2x80x9cdirtierxe2x80x9d processes. MOCVD and CVD processing environments are filled with impurities which readily react with copper. Extraneous materials, such as oxygen and carbon, are readily incorporated into the copper seed layer. This degrades the quality and reliability of the seed layer. The impurities reduce seed layer adhesion to the underlying barrier layer. Additionally, the impurities increase the resistivity of the copper seed layer and degrade the uniformity of the subsequently deposited bulk copper interconnect layer. The impurities also lead to poor bonding with the subsequently formed bulk copper interconnect layer.
In summary, existing processes of copper interconnect formation suffer from a number of drawbacks, including difficulties in forming seed and barrier layers in vias and trenches having high aspect ratios (i.e., deep trenches having narrow trench widths), poor step coverage (non-uniform surface coverage), and void formation in the barrier, seed, and bulk interconnect layers of the damascened process. Additionally, existing techniques exhibit poor adhesion between the barrier and seed layers leading to an increased incidence of void formation at the barrier layer/seed layer interface. This difficulty leads to increased incidence of electromigration and increased incidence of circuit unreliability. Additionally, existing processes are not easily extendible into smaller dimensions (i.e., below 0.1 xcexcm). As a result, there is a need for an improved interconnect structure including improved barrier and seed layers as well as the method of forming these structures and layers.
Accordingly, there is a need for improved processes and semiconductor metallization structures that provide:
enhanced step coverage of the seed and barrier layers in deep sub-0.25-xcexcm vias and trenches;
reduced incidence of void formation at via and trench sidewalls during subsequent bulk copper deposition;
enhanced adhesion between the layers of a barrier layer/seed layer/bulk layer structure;
increased electromigration resistance in interconnect structures; and
extension of the copper damascene process to extremely small dimensions beyond 0.1 xcexcm in width or diameter.
Accordingly, the present invention discloses improved barrier and seed layers as well as methods for constructing them. The present invention also discloses an improved interconnect structure as well as a method for construction.
In accordance with the principles of the present invention, there is provided a new interconnect structure and the method of forming the interconnect structure. The present invention is an interconnect structure having a barrier layer formed over a patterned semiconductor substrate using atomic layer deposition; a pre-seed layer formed using atomic layer epitaxy; a thick seed layer; a bulk copper interconnect layer; and a top sealing layer. The method of the present invention comprises providing a semiconductor substrate having an inlaid circuit pattern on its surface corresponding to a conductor wiring pattern; depositing a layer of barrier material over said surface using atomic layer deposition; depositing a pre-seed layer of conducting material using atomic layer epitaxy; depositing a seed layer of conducting material; depositing a bulk interconnect layer; further processing which may include planarizing said interconnect layer and forming a top sealing layer.
Other features of the present invention are disclosed or apparent in the section entitled xe2x80x9cDETAILED DESCRIPTION OF THE INVENTION.xe2x80x9d